In the area of digital systems, the task of accommodating increasing bus traffic continues to pose a challenge. The primary bottle-neck in most bus transactions appears to be the system bus. The system bus is a bottle-neck primarily because many devices share the same bus and must contend for its resources.
The PCI bus is a high performance, 32-bit or 64-bit bus with multiplexed address and data lines which can accommodate multiple high performance peripherals. The PCI Bus supports burst modes in which a bus transaction may involve an address phase followed by one or more data phases in tandem with a command phase followed by one or more byte enable phases. As such, an external device may require the use of the bus for multiple clock cycles during a bus transaction which can exacerbate bottle-neck problems associated with a system bus. Reference is now made to FIG. 1 which illustrates an overview of a computer system that utilizes the PCI bus. In FIG. 1, computer system 100 comprises host CPU 101, host memory 102, peripheral hardware controller 103, and bridge device 105. Peripheral hardware controller 103 is coupled to host CPU 101 and host memory 102 through PCI bus 104. More particularly, peripheral hardware controller 103 provides an interface between PCI bus 104 and external devices such as disk drivers, display monitors, parallel data port, local area network, wide area network, or the like.
In general, host CPU 101 and external devices may take turns controlling PCI bus 104 in carrying out transactions such as read and write transactions. While a device which takes control of PCI bus 104 to initiate the transaction is known as a "bus master" device, a device at the other end of the transaction is known as a "bus target" (or "slave") device. Information that are involved in bus transactions between devices include data, address, commands, byte enables, and identification of bus master and bus target device.
While a bus may be synchronous or asynchronous, PCI bus is a synchronous bus. In other words, information flowing from the bus master device to the target device and vice versa are synchronized to a system clock such that a bus transaction must take place in an integral number of synchronized clock cycles. In carrying out bus transactions, bus protocols must be followed. These protocols consists mainly of bus mastership, requests for read or write transactions, and acknowledgment of such requests. PCI bus protocols can be found in "The PCI Local Bus Specification Rev 2.1", published by the PCI Special Interest Group, P.O. Box 14070, Portland, Ore. 97214 and incorporated herein by reference.
The PCI bus can be tristated which means that the bus is floated to indicate that it is available for use. When a bus is floated, it generally indicates to devices connected to it that it is available for usage. However, depending on the threshold voltage of a device connected to the bus, the logic value associated with a tristated PCI bus may inadvertently trigger an undesired state in the device connected to the bus. In the Prior Art, to prevent the propagation of invalid data values into a device, flip-flops or latches are implemented inside the device to hold known and unknown data propagated from the bus until it can be determined whether the data is valid or not. Having additional flip-flops or latches for this purpose is not cost efficient.
Hence, there is a need for an apparatus, system, and method to prevent invalid data from propagating into a device connected to the bus without incurring unnecessary added costs.